VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
(3/3)
Current state
CS
H
RAS
X
CA
X
WE Address
Command
DESL
Action
Notes
Write
recovering
X
H
L
X
X
X
Nop ® Enter row active after tDPL
L
L
H
H
H
H
NOP
BST
Nop ® Enter row active after tDPL
Nop ® Enter row active after tDPL
L
L
L
L
L
L
H
H
H
L
L
L
H
L
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
READ/READA
WRIT/WRITA
ACT
Start read, Determine AP
New write, Determine AP
ILLEGAL
8
H
H
L
H
L
3
3
L
PRE/PALL
PEF/SELF
MRS
ILLEGAL
L
H
L
ILLEGAL
L
L
Op-Code
X
ILLEGAL
Write
X
X
X
DESL
Nop ® Enter precharge after tDPL
recovering
with auto
precharge
L
L
H
H
H
H
H
L
X
X
NOP
BST
Nop ® Enter precharge after tDPL
Nop ® Enter precharge after tDPL
L
L
L
L
L
L
H
H
H
L
L
L
H
L
BA,CA,A10
BA,CA,A10
BA,RA
BA,A10
X
READ/READA
WRIT/WRITA
ACT
ILLEGAL
3,8
3
ILLEGAL
H
H
L
H
L
ILLEGAL
3
L
REF/PALL
REF/SELF
MRS
ILLEGAL
3
L
H
L
ILLEGAL
L
L
Op-Code
X
ILLEGAL
Refreshing
X
X
X
DESL
Nop ® Enter idle after tRC
L
H
H
X
X
NOP/BST
Nop ® Enter idle after tRC
L
L
H
L
L
H
L
X
X
X
X
X
X
X
X
READ/WRIT
ILLEGAL
ILLEGAL
ACT/PRE/PALL
L
L
REF/SELF/MRS ILLEGAL
Mode register
accessing
H
X
X
DESL
NOP
Nop ® Enter idle after 2 Clocks
L
H
H
H
X
Nop ® Enter idle after 2 Clocks
ILLEGAL
L
L
L
H
H
L
H
L
L
X
X
X
X
X
BST
READ/WRITE
ILLEGAL
X
ACT/PRE/PALL/ ILLEGAL
REF/SELF/MRS
Note 1. All entries assume that CKE was active (High level)during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive(Low level), the device will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If both banks are idle, and CKE is inactive(Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. IIIegal if t
is not satisfied.
RCD
6. IIIegal if t
is not satisfied.
RAS
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data if t
is not satisfied.
DPL
10. IIIegal if t
is not satisfied.
RRD
Document:1G5-0189
Rev.1
Page12
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
