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VSC870TX 参数 Datasheet PDF下载

VSC870TX图片预览
型号: VSC870TX
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能串行背板收发器 [High Performance Serial Backplane Transceiver]
分类和应用: 线路驱动器或接收器驱动程序和接口接口集成电路
文件页数/大小: 40 页 / 512 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE  
SEMICONDUCTOR CORPORATION  
Data Sheet  
High Performance Serial  
Backplane Transceiver  
VSC870  
2), it stops reading from the parallel interface by setting REN LOW, sets RTM/TCLK HIGH and starts sending a  
repeated sequence of CRQ words to the switch which are arbitrated only on the cycle that they arrive. During this  
operation, the CRQ words are not stored at the switch. If all connections are granted, the transceiver will receive an  
ACK from the switch. If DLYEN/CCKIN is LOW, it sets the REN signal HIGH when it receives the ACK, and sends  
the header word and data to the switch. If DLYEN/CCKIN is HIGH, it waits for N more cycles before it sets REN  
HIGH and then sends header word and data to the switch.  
During the repeated sequence of CRQs described above, different priorities for connections can be established by  
the number of the IDLE words sent between each CRQ words (determined by the CT[2:0]). The number of IDLEs  
after each CRQ word can range from 0-7 as shown in the table below. Generally, the more often a CRQ is received by  
the switch, the higher the probability that this connection will be granted.  
Number of  
IDLE Words  
Number of  
IDLE Words  
CT[2:0]  
CT[2:0]  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
0
1
2
3
1 0 0  
1 0 1  
1 1 0  
1 1 1  
4
5
6
7
The functional timing diagram for camp-on mode with DLYEN/CCKIN set LOW is shown in figure 3. There are  
a minimum of 9 word clock cycles between loading the CRQ into the transceiver and the signal REN going HIGH (to  
start sending the data packet D0, D1, D2 etc.). This time will be longer if the requested output is busy or the port card  
is located further from the switch card. For multicast, the switch will reserve any available outputs and accumulate  
them as more CRQ commands are processed. This continues until all connections are reserved. At this point an ACK  
signal is sent back to the transceiver.  
Figure 3: Camp-on with Priority Transmitter Functional Timing (no early arbitration)  
WCLK  
Minimum of 9 clock cycles  
TXIN[31:0]  
TXTYP[1:0]  
CRQ  
3
D1 D2  
D3 D4 D5  
HDR  
2
D0  
1
ACK/RCLK  
REN  
RTM/TCLK  
© VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012  
Tel: (800) VITESSE FAX: (805) 987-5896 Email: prodinfo@vitesse.com  
Internet: www.vitesse.com  
G52190-0, Rev 4.1  
01/05/01  
Page 19  
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