VSC864A-2
VITESSE
Data Sheet
200 Mb/s 64 x 64
Crosspoint Switch
The Write mode is used to alter any one or all signal paths. During Write mode, inputs A0 - A5 select which
output channel's control register will be altered (also by a binary numerical representation). Inputs D0- D5
describe the new input signal to be selected for that channel. When a high pulse is applied to LOCAL STROBE,
D0- D5 and the TRI bit is transferred into a holding latch. After some or all control registers are programmed, a
high pulse is applied to GLOBAL STROBE to transfer the information from the holding latch into all the con-
trol registers. In this way the entire crosspoint switch can be reconfigured simultaneously.
The Read mode is a diagnostic feature used to examine the data stored in any one control register and its
corresponding 64:1 multiplexer output. The control register to be examined is selected by inputs S0- S5 (by a
binary numerical representation). When a high pulse is applied to the TEST STROBE, the contents of the
selected control register will be displayed at the Q0- Q6 outputs and the corresponding 64:1 mux output will
appear at the QD output. When TEST STROBE is "low" the Q bus has all low outputs (which is equivalent to
being tri-stated).
The VSC864A-2 can be configured to run in either synchronous clocked mode or asynchronous flow-
through mode. This feature is controlled by the C/FT input. When C/FT is high, the chip is in clocked mode and
will require an input clock at its CK pin. In this mode all input and output data is registered. When C/FT is low
the chip is in flow-through mode and will ignore the CK input. In clocked mode, the outputs on the monitor bus
(Q0- Q6, and QD), and input data (I0 - I63) are registered by the master clock (CK).
Figure 1: Block Diagram
I0-I63
x64
2:1
Mux
x64
64:1
Mux
2:1
Mux
Z0
CLK
C/FT
7-bit
Control
Latch
7-bit
Addr-able
Holding Latch
D0-D5,TRI
64:1
Mux
2:1
Mux
Z1
A0-A5
6:64
Decode
7-bit
Control
Latch
7-bit
Addr-able
Holding Latch
GLOBAL STROBE
LOCAL STROBE
64:1
Mux
QD
TEST STROBE
S0-S5
64:1
Mux
x7
Q0-Q6
Page 2
®
VITESSE
Semiconductor Corporation
G52132-0 Rev. 2.0
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
