VITESSE
Data Sheet
Table 4: Pin Description
Pin #
12-16, 20-30, 35-45, 49-53,184-
188, 192- 202, 207-217, 221-225
VSC864A-2
200 Mb/s 64 x 64
Crosspoint Switch
Name
I
0
- I
63
I/O
I
Description
The 64 ECL signal inputs.
ECL input containing Tristate data to be loaded into a 64:1
Mux holding latch. (Tristate = HIGH) Combined with a
control register's destination address. Used to tristate the
corresponding output.
ECL inputs containing the destination address to be loaded
into the 64:1 Mux holding latch.
ECL inputs containing the address of the 64:1 Mux holding/
control latch to be programmed.
Active HIGH, ECL input used to load the D0-D5 and TRI
data into the 64:1 Mux holding latch.
Active HIGH, ECL input used to load destination addresses
to all 64:1 S Mux control latches simultaneously from the
data contained in their corresponding holding latches.
ECL inputs containing the address of the control latch to be
observed at the QD output when the TEST STROBE is
HIGH.
Active HIGH, ECL input used to enable Test Mode and
observation of a selected 64:1 Mux control latch's
destination address.
ECL input used to enable Clocked or Flow-through Mode
(Clocked = HIGH/Flow-Thru = LOW).
ECL clock input for Clocked Mode.
11
TRI
1
5-10
178-183
177
D
0
- D
5
A
0
- A
5
LOCAL
STROBE
GLOBAL
STROBE
I
I
I
34
I
54-59
S
0
- S
5
TEST
STROBE
I
60
I
I
I
206
203
68, 71, 73, 78, 80, 83, 85, 88,
92,95,97,100,102,107,109,112,
126, 129, 131, 136,138, 141,143,
148, 150, 153, 155,158, 162, 165,
167, 170, 240, 243, 245, 250, 252,
255, 257, 260, 264, 267, 269, 272,
274, 279, 281, 284, 298, 301, 303,
308, 310, 313, 315, 320, 322, 325,
327, 330, 334, 337, 339, 342
296
114,117,121,124,286,289,293
C/FT
CK
Z
0
- Z
63
O
The 64 ECL signal outputs.
QD
Q
0
- Q
6
O
O
ECL output used to observe the output of a selected 64:1 Mux in
Test Mode.
ECL outputs containing the selected 64:1 Mux control register’s
destination address and TRI bit in Test Mode
G52132-0 Rev. 2.0
®
VITESSE
Semiconductor Corporation
Page 7
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
