VSC8601 Datasheet
Design Considerations
PhyWrite (PortNo, 31, 0x52B5); // Select internal register page
PhyWrite (PortNo, 16, 0xA7F8); // Request read of internal register
PhyWriteMsk (PortNo, 17, 0x0018, 0x0018); // Set for forced 100BASE-TX
PhyWriteMsk (PortNo, 18, 0, 0); // Necessary read & re-write register 18
PhyWrite (PortNo, 16, 0x87F8); // Write back modified internal register
PhyWrite (PortNo, 31, 0); // Select main register page
When returning from forced 100BASE-TX mode to auto-negotiation mode, use the
following script to restore the standard method that VSC8601 uses to perform
crossover detection:
PhyWrite (PortNo, 31, 0x52B5); // Select internal register page
PhyWrite (PortNo, 16, 0xA7F8); // Request read of internal register
PhyWriteMsk (PortNo, 17, 0x0000, 0x0018); // Set for auto-negotiation
PhyWriteMsk (PortNo, 18, 0, 0); // Necessary read & re-write register 18
PhyWrite (PortNo, 16, 0x87F8); // Write-back modified internal register
PhyWrite (PortNo, 31, 0); // Select main register page
Note It is not important which order is used for writes to the SMI register with respect
to writes to Register 0, which disable and enable the auto-negotiation feature.
8.4
Default 10Base-T Settings Are Marginal and Cause
MAU Test Failure
Issue: Default 10Base-T settings are marginal for PHY silicon and magnetic module
variations.
Implications: It often causes the output 10Base-T signal to violate the IEEE waveform
templates.
Workaround: During device initialization, use the following script. For more information,
see PHY API Software and Programmers Guide, which is available on the Vitesse Web
site at www.vitesse.com.
PhyWrite (PortNo, reg_num(dec), 16_bit_unsigned_data(hex))
PhyRead (PortNo, reg_num(dec))
~ -- Logical NOT
& -- Logical AND
| -- Logical OR
= -- Assign value to variable
PhyWrite (PortNo, 31, 0x52b5); // Select internal register page
PhyWrite (PortNo, 18, 0x9e); // Necessary write of internal register
PhyWrite (PortNo, 17, 0xdd39); // Necessary write of internal register
PhyWrite (PortNo, 16, 0x87aa); // Necessary write of internal register
PhyWrite (PortNo, 16, 0xa7b4); // Necessary write of internal register
reg = PhyRead (PortNo, 18); // Read internal reg. and assign it to var.
PhyWrite (PortNo, 18, reg); // Necessary write of internal register
reg = PhyRead (PortNo, 17); // Read internal reg. and assign it to var.
reg = (reg & ~0x003f) | 0x003c;// Modify variable value
PhyWrite (PortNo, 17, reg); // Write back modified internal register
Revision 4.1
September 2009
Page 97
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
