VSC8601 Datasheet
Package Information
7.2
Thermal Specifications
Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2
and have been modeled using a four-layer test board with two signal layers, a power
plane, and a ground plane (2s2p PCB). For more information, see the JEDEC standard.
Table 86.
Thermal Resistances
θJA (°C/W) vs. Airflow (ft/min)
Part Order Number
θJC
θJB
0
100
200
VSC8601XKN
18.5(1)
22
33
30
28
6.4(2)
1. Simulated on the top of the mold compound with the exposed pad soldered to a ground pad on
the PCB.
2. Calculated on the exposed pad soldered to a ground pad on the PCB.
To achieve results similar to the modeled thermal resistance measurements, the
guidelines for board design described in the JEDEC standard EIA/JESD51 series must be
applied. For information about specific applications, see the following:
EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct
Thermal Attachment Mechanisms
EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface
Mount Packages
EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal
Measurements
EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal
Measurements
EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal
Measurements
7.3
Moisture Sensitivity
This device is rated moisture sensitivity level 3 or better as specified in the joint IPC
and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and
JEDEC standard.
Revision 4.1
September 2009
Page 95
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
