VSC8601 Datasheet
Electrical Specifications
Table 73.
AC Characteristics for Device Reset (continued)
Parameter
Symbol
Minimum Maximum Unit Condition
Soft reset (pin) assertion
tSRESET_ASSERT
tSRESET_DEASSERT
4
4
ms
ms
Soft reset (pin)
de-assertion
Reset rise time
tRST_RISE
0
25
ms If REG_EN pin = 0
ms If REG_EN pin = 1
Measured from a 10% level to a
90% level
Supply stable time
tVDDSTABLE
tSWAIT
10
ms
Wait time between soft
reset pin de-assert and
access of the SMI interface
4
µs
µs
Registers 28.1 = 1, 21E.14 = 0
Registers 28.1 = 0, 21E.14 = 0
300
200
200
ms Registers 28.1 = 0, 21E.14 = 1
ms Registers 28.1 = 1, 21E.14 = 1
Soft reset MII register 0.15
assertion
tSREG_RESET
tSREG_WAIT
100
ns
Wait time between Soft
Reset (MII Register 0.15)
de-assert and access to the
SMI interface
4
µs
µs
Registers 18.1 = 1, 21E.14 = 0
Registers 18.1 = 0, 21E.14 = 0
300
200
200
ms Registers 18.1 = 0, 21E.14 = 1
ms Registers 18.1 = 1, 21E.14 = 1
Figure 20.
Reset Timing
tVDDSTABLE
VDD33
REFCLK
tRST_RISE
tWAIT
tRESET
NRESET
NSRESET
tSRESET_DEASSERT
tSRESET_ASSERT
tSREG_WAIT
tSWAIT
tSREG_RESET
Soft Reset
(MII Register 0.15)
Undefined State
MDC
MDIO
Note The NRESET and NSRESET are mutually exclusive.
Revision 4.1
September 2009
Page 79
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
