VSC8601 Datasheet
Configuration
Table 8.
Mode Control, Address 0 (0x00) (continued)
Bit
Name
Access Description
Default
11
Power-down
R/W
1 = Power-down enabled.
If power-down is enabled, the RGMII’s
0
in-band signaling is disabled. When this bit
is set, RGMII in-band signaling does not
function.
10
9
Isolate
R/W
R/W
1 = Disable MAC interface outputs and
ignore MAC interface inputs.
0
0
Restart
auto-negotiation
This is a self-clearing bit.
1 = Restart auto-negotiation on media
interface.
8
Duplex
R/W
1 = Full-duplex.
0 = Half-duplex.
0
7
6
Collision test enable
R/W
R/W
1 = Collision test enabled.
See bit 13 above.
0
1
MSB for speed
selection
5:0
Reserved
000000
4.2.2
Mode Status
The register at 1.01.15:0 in the device main registers space displays the currently
enabled mode setting. The following table lists possible readouts of this register.
Table 9.
Mode Status, Address 1 (0x01)
Bit
Name
Access Description
Default
15
100BASE-T4
capability
RO
RO
RO
RO
RO
RO
RO
RO
1 = 100BASE-T4 capable.
0
14
13
12
11
10
9
100BASE-X FDX
capability
1 = 100BASE-X FDX capable.
1 = 100BASE-X DDX capable.
1 = 10BASE-T FDX capable.
1 = 10BASE-T HDX capable.
1 = 100BASE-T2 FDX capable.
1 = 100BASE-T2 HDX capable.
1
1
1
1
0
0
1
100BASE-X HDX
capability
10BASE-T FDX
capability
10BASE-T HDX
capability
100BASE-T2 FDX
capability
100BASE-T2 HDX
capability
8
Extended status
enable
1 = Extended status information present in
register 15.
7
6
Reserved
RO
RO
0
1
Preamble
suppression
capability
1 = MF preamble may be suppressed.
0 = MF always required.
5
Auto-negotiation
complete
RO
1 = Auto-negotiation complete.
0
Revision 4.1
September 2009
Page 40
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
