VSC8601 Datasheet
Configuration
4.1.1
4.1.2
Reserved Registers
For main registers 16 through 31 and extended page registers 16E through 30E, any
bits marked as “Reserved” should be processed as read only and their states as
undefined.
Reserved Bits
In writing to registers with reserved bits, use a “read-modify-then-write” technique,
where the entire register is read but only the intended bits to be changed are modified.
Reserved bits cannot be changed and their read state cannot be considered static or
unchanging.
4.2
IEEE Standard and Main Registers
In the VSC8601 device, the standard registers’ page space consists of the IEEE
standard registers and the Vitesse standard registers. The following table lists the
names of the registers associated with the addresses as dictated by the IEEE standard.
Table 6.
IEEE 802.3 Standard Registers
Register Address Register Name
0
1
Mode control
Mode status
2
PHY identifier 1
3
PHY identifier 2
4
Auto-negotiation advertisement
Auto-negotiation link partner ability
Auto-negotiation expansion
Auto-negotiation next-page transmit
Auto-negotiation link partner next-page receive
1000BASE-T control
1000BASE-T status
5
6
7
8
9
10
11
12
13
14
15
Reserved
Reserved
Reserved
Reserved
1000BASE-T status extension 1
The following table lists the names of the registers in the main page space of the
device. These registers are accessible only when register address 31 is set to 0x0000.
Table 7.
Main Registers
Register Address Register Name
16
17
100BASE-TX status extension
1000BASE-T status extension 2
Revision 4.1
September 2009
Page 38
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
