VSC8601 Datasheet
Configuration
Table 7.
Main Registers (continued)
Register Address Register Name
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Bypass control
Receive error counter
False carrier sense counter
Disconnect counter
Extended control and status
Extended PHY control 1
Extended PHY control 2
Interrupt mask
Interrupt status
LED control
Auxiliary control and status
Delay skew status
Reserved
Extended register page access
4.2.1
Mode Control
The device register at memory address 0.00.15:0 controls several aspects of VSC8601
functionality. The following table lists the available bit settings in this register and what
they control.
Table 8.
Mode Control, Address 0 (0x00)
Bit
Name
Access Description
Default
15
Software reset
R/W
This is a self-clearing bit that restores all
0
serial management interface (SMI) registers
to their default state, except for sticky and
super sticky bits.
1 = Reset asserted.
0 = Reset de-asserted.
You must wait 4 µs after setting this bit to
initiate another SMI register access.
14
Loopback
R/W
1 = Loopback enabled.
0
0 = Loopback disabled.
When loop back is enabled, the device
functions at the current speed setting and
with the current duplex mode setting (bit 8
of this register).
13, 6 Forced speed
selection
R/W
R/W
LSB = bit 13, MSB = bit 6.
00 = 10 Mbps.
01 = 100 Mbps.
10 = 1000 Mbps.
11 = Reserved.
10
1
12
Auto-negotiation
enable
1 = Auto-negotiation enabled.
0 = Auto-negotiation disabled.
Revision 4.1
September 2009
Page 39
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
