VSC8601 Datasheet
Functional Descriptions
includes all IEEE-required signals (TMS, TCK, TDI, and TDO), in addition to the optional
asynchronous reset signal NTRST.
The following illustration shows the TAP and boundary-scan architecture.
Figure 15.
Test Access Port and Boundary-Scan Architecture
Boundary-Scan
Register
Device Identification
Register
Bypass Register
TDO
Mux,
DFF
Control
Instruction Register,
Instruction Decode,
Control
TDI
Control
Select
TMS
NTRST
TCK
Test Access Port
Controller
tdoenable
After a TAP reset, the Device Identification register is serially connected between TDI
and TDO by default. The TAP Instruction register is loaded either from a shift register
(when a new instruction is shifted in) or, if there is no new instruction in the shift
register, a default value of 0110 (IDCODE) is loaded. Using this method, there is always
a valid code in the instruction register, and the problem of toggling instruction bits
during a shift is avoided. Unused codes are mapped to the BYPASS instruction.
3.13.8
JTAG Instruction Codes
The VSC8601 device supports the following instruction codes:
EXTEST Allows testing of off-chip circuitry and board-level interconnections by
sampling input pins and loading data onto output pins. Outputs are driven by the
contents of the boundary-scan cells, which have to be updated with valid values (with
the PRELOAD instruction) prior to the EXTEST instruction.
Revision 4.1
September 2009
Page 34
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
