VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
VSC8140
Package Information
128 PQFP Package Drawings
PIN 128
PIN 1
PIN 102
Key
mm
Tolerance
A
A1
A2
D
2.35
0.25
2.00
17.20
14.00
23.20
20.00
.88
MAX
MAX
+.10
RAD. 2.92 ± .50
(2)
±.20
E
E
1
D1
E
±.10
±.20
EXPOSED
INTRUSION
0.127 MAX.
E1
L
±.10
2.54 ± .50
EXPOSED
HEATSINK
+.15/-.10
BASIC
±.05
e
.50
b
.22
PIN 38
PIN 64
q
0°-7°
.30
D
1
R
TYP
TYP
D
R1
.20
TOP VIEW
10° TYP.
A
2
A
A
e
1
10° TYP.
R
R1
θ1
STANDOFF
A
1
.25
A
Notes: 1) Drawing is not to scale
2) All dimensions in mm
3) Package represented is
also used for the 64,
θ
b
MAX.
0.17
NOTES:
LEAD COPLANARITY
80, & 100 PQFP packages.
Pin count drawn does
not reflect the 128 Package.
Package #: 101-322-5
Issue #: 2
L
G52251-0, Rev. 4.0
9/6/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 23
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
