VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8117
Table 15: Pin Identification
Signal
Pin
I/O
Level
Pin Description
LOSPECL
VDD
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
I
PECL
+3.3V
GND
TTL
Loss of Signal Control- Single ended PECL input; active low
+3.3V Power Supply
VSS
Ground
REFCLK
VSSA
VDDA
CP1
I
Reference clock input, refer to table 10
Analog Ground (CMU)
GND
+3.3V
Analog
Analog
Analog
Analog
+3.3V
GND
GND
GND
+3.3V
+3.3V
TTL
Analog Power Supply (CMU)
CMU external capacitor (see Figure 6, and Table 1)
CMU external capacitor (see Figure 6, and Table 1)
CMU external capacitor (see Figure 6, and Table 1)
CMU external capacitor (see Figure 6, and Table 1)
Analog Power Supply (CRU)
Analog Ground (CRU)
CN1
CN2
CP2
VDDA
VSSA
VSS
Ground
VSS
Ground
VDD
+3.3V Power Supply
VDD
+3.3V Power Supply
TXLSCKOUT
TXIN7
TXIN6
VSS
O
I
Transmit byte clock out
TTL
Transmit input data bit7
I
TTL
Transmit input data bit6
GND
TTL
Ground
TXIN5
TXIN4
TXIN3
TXIN2
TXIN1
TXIN0
STS12
CRUREFSEL
VDD
I
I
I
I
I
I
I
I
Transmit input data bit5
TTL
Transmit input data bit4
TTL
Transmit input data bit3
TTL
Transmit input data bit2
TTL
Transmit input data bit1
TTL
Transmit input data bit0
TTL
155Mb/s or 622Mb/s mode select, refer to table 10
Selects between CMU’s or CRU’s REFCLK
+3.3V Power Supply
TTL
+3.3V
Equipment loopback, loops low speed byte wide transmit
input data to receive output bus
EQULOOP
62
I
TTL
Facility loopback, loops high speed receive data and clock
directly to transmit outputs.
FACLOOP
CRUEQLP
63
64
I
I
TTL
TTL
Loops TXDATAOUT to the CRU replacing RXDATAIN+/-
Page 16
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52221-0, Rev 4.1
1/8/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
