VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8117
Package Pin Descriptions
Table 15: Pin Identification
Signal
RESET
Pin
I/O
Level
Pin Description
1
I
I
I
TTL
TTL
Resets frame detection, dividers, controls; active high
Enable loop timing operation; active HIGH
Reference clock frequency select, refer to table 10
+3.3V or +5V Power Supply for PECL I/Os
Transmit output, high speed differential data +
Transmit output, high speed differential data -
Enables internal LOS detection (active low).
Receive high speed differential clock input+
Receive high speed differential clock input-
+3.3V or +5V Power Supply for PECL I/Os
Out Of Frame; Frame detection initiated with high level
Disable on-chip clock recovery unit; active high
Receive high speed differential data input+
Receive high speed differential data input-
+3.3V Power Supply
LOOPTIM0
CMUFREQSEL
VDDP
2
3
TTL
4
+3.3/+5V
PECL
PECL
TTL
TXDATAOUT+
TXDATAOUT-
LOSDETEN_
RXCLKIN+
RXCLKIN-
VDDP
5
O
O
I
6
7
8
I
PECL
PECL
+3.3/+5V
TTL
9
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OOF
I
I
I
I
DSBLCRU
RXDATAIN+
RXDATAIN-
VDD
TTL
PECL
PECL
+3.3V
PECL
PECL
+3.3V
TTL
REFCLKP+
REFCLKP-
VDD
I
I
PECL reference clock input+
PECL reference clock input-
+3.3V Power Supply
RXOUT0
RXOUT1
VSS
O
O
Receive output data bit0
TTL
Receive output data bit1
GND
TTL
Ground
RXOUT2
RXOUT3
RXOUT4
RXOUT5
RXOUT6
RXOUT7
VSS
O
O
O
O
O
O
Receive output data bit2
TTL
Receive output data bit3
TTL
Receive output data bit4
TTL
Receive output data bit5
TTL
Receive output data bit6
TTL
Receive output data bit7
GND
TTL
Ground
RXLSCKOUT
FP
O
O
Receive byte clock output
TTL
Frame detection pulse
VDD
+3.3V
TTL
+3.3V Power Supply
CRUREFCLK
I
Optional external CRU reference clock @77.76MHz
G52221-0, Rev. 4.1
1/8/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 15
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