VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8117
Table 11: Clock Multiplier Unit Performance
Name
Description
Reference clock duty cycle
Reference clock jitter (RMS) @ 77.76 MHz ref (1)
Reference clock jitter (RMS) @ 19.44 MHz ref (1)
Reference clock frequency tolerance (2)
Min
Typ
Max
Units
RCd
RCj
RCj
RCf
40
60
13
5
%
ps
ps
-20
+20
ppm
(1)
(2)
These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements
(< 10 mUIrms)
Needed to meet SONET output frequency stability requirements
Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.
AC Characteristics
Table 12: PECL and TTL Outputs
Parameters
Description
Min
Typ
Max
Units
Conditions
10-90%
TR,TTL
TF,TTL
TR,PECL
TF,PECL
TTL Output Rise Time
TTL Output Fall Time
PECL Output Rise Time
PECL Output Fall Time
—
—
—
—
2
—
—
—
—
ns
ns
ps
ps
1.5
350
350
10-90%
20-80%
20-80%
DC Characteristics
Table 13: PECL and TTL Inputs and Outputs
Parameters
Description
Min
Typ
Max
Units
Conditions
Output HIGH
voltage (PECL)
VOH
—
—
—
VDDP – 0.9V
—
V
—
—
Output LOW
voltage (PECL)
VOL
0.7
1.1
V
V
O/P Common
Mode Range
(PECL)
VOCM
—
—
VDDP – 1.3V
1300
—
Differential
Output Voltage
(PECL)
∆VOUT75
600
mV
75Ω to VDDP – 2.0 V
Page 12
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52221-0, Rev 4.1
1/8/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
