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VSC8117QP1 参数 Datasheet PDF下载

VSC8117QP1图片预览
型号: VSC8117QP1
PDF下载: 下载PDF文件 查看货源
内容描述: ATM / SONET / SDH 155分之622 Mb / s的收发器复用/解复用,集成时钟发生器和时钟恢复 [ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery]
分类和应用: 时钟发生器ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 22 页 / 408 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8117
AC Timing Characteristics
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Figure 8: Receive High Speed Data Input Timing Diagram
T
RXCLK
RXCLKIN+
RXCLKIN-
T
RXSU
RXDATAIN+
RXDATAIN-
T
RXH
Table 2: Receive High Speed Data Input Timing Table
(STS-12
Operation)
Parameter
T
RXCLK
T
RXSU
T
RXH
Receive clock period
Serial data setup time with respect to RXCLKIN
Serial data hold time with respect to RXCLKIN
Description
Min
-
400
100
Typ
1.608
-
-
Max
-
-
-
Units
ns
ps
ps
Table 3: Receive High Speed Data Input Timing Table
(STS-3
Operation)
Parameter
T
RXCLK
T
RXSU
T
RXH
Receive clock period
Serial data setup time with respect to RXCLKIN
Serial data hold time with respect to RXCLKIN
Description
Min
-
1.5
1.5
Typ
6.43
-
-
Max
-
-
-
Units
ns
ns
ns
Figure 9: Transmit Data Input Timing Diagram
T
CLKOUT
TXLSCKOUT
T
INSU
T
INH
TXIN [7:0]
G52221-0, Rev. 4.1
1/8/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 9