VITESSE
SEMICONDUCTOR CORPORATION
Target Specification
VSC8115
Absolute Maximum Ratings
(1)
STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit
Power Supply Voltage (V
DD
) Potential to GND.................................................................................-0.5V to +4V
DC Input Voltage (LVPECL Inputs)..................................................................................... -0.5V to V
DD
+ 0.5V
DC Input Voltage (LVTTL Inputs) ....................................................................................... -0.5V to V
DD
+ 0.5V
Output Current (LVDS or LVPECL Outputs).......................................................................................... +/-50mA
Case Temperature Under Bias.........................................................................................................-55
o
to +125
o
C
Storage Temperature .................................................................................................................... -65
o
C to +150
o
C
Maximum Input ESD (Human Body Model)
High Speed Outputs (pins 11, 12, 13, & 14) .................................................................................... 500V
All Other Pins ................................................................................................................................. 1500V
Note: Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing
permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Power Supply Voltage (V
DD
)................................................................................................................+3.3V
±
5
%
Industrial Operating Ambient Temperature Range under Bias ......................................................... -40
o
to 85
o
C
Commercial Operating Ambient Temperature Range under Bias ....................................................... 0
o
to 70
o
C
Package Pin Descriptions
Figure 4: Pin Diagram
VDDA
DATAIN+
DATAIN-
VSSA
LOCKDET
STS12
REFCLK
LOCKREFN
VSS
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDDA
VSSA
CAP+
CAP-
BYPASS
SD
DATAOUT+
DATAOUT-
CLKOUT+
CLKOUT-
G52272-0, Rev. 1.1
9/29/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 9
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
