VITESSE
SEMICONDUCTOR CORPORATION
STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit
Target Specification
VSC8115
AC Characteristics
Table 2: Performance Specifications
Parameters
VCO Center Frequency
CRU’s Reference Clock Frequency
Tolerance
OC-12/STS12 Capture Range
Clock Output Duty Cycle
Acquisition Lock Time OC-12/STS-12
LVDS Output Rise & Fall Times
CLKOUT+/- Jitter Generation
OC-12/STS-12 Jitter Tolerance
Min
—
-250
—
45
—
—
—
Typ
622.08
—
±
500
—
—
—
0.005
Max
—
+250
—
55
16
600
0.01
Units
MHz
ppm
ppm
% of UI
µs
ps
U.I.
Conditions
With respect to the fixed
reference frequency
20% Minimum transition
density
Valid REFCLK and device
already powered up
10% to 90%, with 100Ω & 5pF
capacitive equivalent load
No more than 14ps rms jitter on
DATAIN+/-
Sinusoidal input jitter of
DATAIN+/- from 250KHz to
5MHz
0.5
—
—
U.I.
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52272-0, Rev. 1.1
9/29/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
