VITESSE
SEMICONDUCTOR CORPORATION
Target Specification
STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit
VSC8115
Table 10: Pin Identification
Signal
I/O
I
Level
Pin Description
Receive data in. The high speed output clock (CLKOUT+/-) is
DATAIN+/-
LVPECL
recovered from this high speed differential input data.
High speed differential data out. This is the retimed version of the
DATAOUT+/-
O
LVDS/LVPECL receive data input (DATAIN+/-). Can be configured as either LVDS
or LVPECL signal.
High speed differential clock out This clock is recovered from the
LVDS/LVPECL receive data input (DATAIN+/-). Can be configured as either LVDS
or LVPECL signal.
CLKOUT+/-
STS12
O
I
STS-12 or STS-3 mode selection. Set HIGH to select the STS-12
LVTTL
operation. Set LOW to select the STS-3 operation.
Lock to REFCLK input. When set LOW, it holds the CLKOUT+/-
LOCKREFN
I
LVTTL
LVPECL
LVTTL
output to within +500ppm of the REFCLK input, and it forces the
DATAOUT+/- output to the LOW state.
Signal Detect. SD should be connected to the SD output on the
optical module. SD is active HIGH. When SD is set HIGH, it means
that there is sufficient optical power. When SD is set LOW to
indicate loss of signal condition, the CLKOUT+/- output signal will
be held to within +500ppm of the REFCLK input; in additions, the
DATAOUT+/- will be held in the LOW state.
SD
I
I
19.44 MHz local reference clock input for the CRU. REFCLK is used
for the PLL phase adjustment during power up, and it also serves as a
stable clock source in the absence of serial input data.
REFCLK
Active HIGH to indicate that PLL is locked to serial data input, and
valid clock and data are present at the serial outputs (DATAOUT+/-
and CLKOUT+/-). The LOCKDET will go inactive under the
following conditions:
LOCKDET
O
LVPECL
(1). If SD is set LOW.
(2). If LOCKREFN is set LOW.
(3). If the VCO has drifted away from the local reference
clock REFCLK by more than 500 ppm.
BYPASS
I
I
LVTTL
Analog
Used for production test. Set to VSS for normal operation.
External loop filter pins. The loop filter capacitor should be
connected to these pins. The capacitor value should be 1.0uF +10%
tolerance.
CAP+/CAP-
+3.3V Power Supply for low speed I/O’s and on-chip digital CMOS
blocks.
VDD
+3.3V
VSS
GND
+3.3V
GND
Ground pin for low speed I/O’s and on-chip digital CMOS blocks
+3.3V Power Supply for high speed I/O’s and on-chip PLL blocks.
Ground pins for high speed I/O’s and on-chip PLL blocks.
VDDA
VSSA
G52272-0, Rev. 1.1
9/29/00
Page 10
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741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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