VITESSE
SEMICONDUCTOR CORPORATION
STS-12/STS-3 Multi Rate
Clock and Data Recovery Unit
Table 6: LVDS Differential Outputs
Parameters
V
OCM
∆
V
OUT
Target Specification
VSC8115
Description
Common Mode
voltage
Differential
Output Swing
Min
1.0
350
Typ
1.35
500
Max
1.7
750
Units
V
mV
Conditions
100Ω PAD to
PADN
100Ω PAD to
PADN
Table 7: LVPECL Differential Outputs
Parameters
V
OCM
∆
V
OUT
Description
Common Mode
voltage
Differential
Output Swing
Min
1.12
400
Typ
-
-
Max
2.0
800
Units
V
mV
Conditions
50Ω to (VDD - 2V)
50Ω to (VDD - 2V)
Table 8: LVTTL Inputs
Parameters
V
IH
V
IL
I
IH
I
IL
Description
Input HIGH voltage
Input LOW voltage
Input HIGH current
Input LOW current
Min
2.0
0
-50
-50
Typ
—
—
---
---
Max
VDD
0.8
50
50
Units
V
V
µA
µA
Conditions
—
—
V
IN
= 2.7V, V
DD
=MAX
V
IN
= 0.5V, V
DD
=MAX
Power Dissipation
Table 9: Power Supply Currents
Parameter
I
DD
P
D
Power dissipation
Description
Power supply current from V
DD
(Typ)
57
188.1
(Max)
80
277
Units
mA
mW
Page 8
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52272-0, Rev. 1.1
9/29/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
