VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8109
PRBS Mode
155/622 Mhz 16 Channel PRBS
Generator and Comparator.
The normal PRBS mode is initialized with LOAD_PAT as described above. Each bit is treated as one error,
i.e. if three bits in one word have the wrong value, the counter will count it as three distinct errors rather than
just one error per word.
PRBS with Frame Mode
If PRBS with frame mode is used, the frame detector indentifies the frame and puts the Error Accumulator
on hold. The frame bits A1 and A2 are replacing the PRBS bits, the VSC8109 would normally treat these frame
bits as errors in the PRBS stream. The hold signal is released as soon as the PRBS pattern returns.
Static Signal Mode and Square Wave Generation Mode
These modes are not supported by the error detection unit.
Error Detection Unit
The error detection unit counts the total number of errors in all 16 channels. The result is stored in a 16 bit
counter where bit 15 is the MSB and bit 0 is the LSB.. This counter can be selected on the output ERR_C[8:0]
using the control signal CNT_SEL[1:0]. The bit ERR_C[8] is an active high overflow bit that indicates error
overflow in the selected 8-bit output register. There are two error counter modes:
Synchronous Counter Mode
The synchronous counter is updated every RCK +/- clock cycle.. The content of bit [15:8] or bit [7:0] can
be selected to appear on the output ERR_C[8:0] using CNT_SEL[1:0]. (See table 5)
Gated Counter Mode
The outputs of the synchronous counter will change unpredictably and will make design of robust off-chip
parallel read logic difficult. The contents of the synchronous counter can be sampled and stored in readout reg-
isters by use of a slower gating signal, either internally or externally provided. If internal gate mode is chosen,
(GATE_SEL = ‘1’), the VSC8109 will generate the gate signal itself every 2
30
RCK +/- clock cycle. If external
gate mode is selected (GATE_SEL = ‘0’) the result from the synchronous counter is stored in the gated counter
when the GATE signal is sampled by at least one RCK +/-clock cycle. (The GATE signal should always be zero
otherwise) The synchronous counter is reset each time a gated counter is loaded regardless if internal or external
gate mode is used. This allows the gated counter to display the number of bit errors that occurred since the pre-
vious gate sample. Note that there is a six clock cycle delay before the stored data in the B-counter is visible on
the ERR_C output if external gate is used and GATE = ‘1’.
G52207-0, Rev. 3.0
4/3/98
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VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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