VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8109
PRBS Mode
155/622 Mhz 16 Channel PRBS
Generator and Comparator.
This mode generates a PRBS pattern of a selectable length determined by LEN_SEL[1:0] (See Table 2).
The options are 2
7
-1, 2
15
-1, 2
23
-1 and 2
31
-1, indicating the number of clock cycles required for the pattern to
repeat itself. The output signal PRBS_SYNC is a pulse generated in the end of each full pattern cycle.
Table 2: PRBS Options and Polynomials
Mode
2
7
-1
2
15
-1
2
23
-1
2
31
-1
LEN_SEL[1]
0
0
1
1
LEN_SEL[0]
0
1
0
1
Generation Polynomial
1 + X
6
+ X
7
1 + X
14
+ X
15
1 + X
18
+ X
23
1 + X
28
+ X
31
PRBS_IN initializes the transmit PRBS generator. The value of PRBS_IN must always be ‘0’ except during
initialization of the PRBS, when PRBS_IN must be logic ‘1’ for at least 32 TCK+/- clock cycles before it
returns to ‘0’ again. The LOAD_PAT signal works in the same manner to initialize the receiver side. Other
PRBS signals are described in the Signal Interface section.(See Table 5)
PRBS with Frame Mode
This mode is similar to the standard PRBS mode, with the exception that a STS-192/STM-64 frame is
inserted- the A1 and A2 bytes replace an equal number of bytes in the PRBS sequence. The receiver detects
these frame bits as non-PRBS, and does not treat them as bit-errors. The error counter is set to hold mode until
the PRBS sequence continues.
Static Signal Mode
The VSC8109 can place a static output pattern on each of the 16 channels. The static signal register is pro-
grammed in the same way as the bypass control register. The WRD_SRC[7:0] data bus is set to the desired out-
put word and latched into registers driving the internal mode selector. This is done with a clock pulse on the
LD_WRD_U and LD_WRD_L inputs. LD_WRD_U maps to channels Q[15:8] and LD_WRD_L maps to chan-
nels Q[7:0]. This is not a bit error rate calculation mode.
Square Wave Generation Mode
This mode generates a square wave output with selectable frequency (See Table 3). The square wave signal
is output simultaneously on all 16 output channels. This is not a bit error rate calculation mode.
Table 3: Square Wave Rates
Frequency
TCKP/2
TCKP/4
TCKP/8
TCKP/16
LEN_SEL[1]
0
0
1
1
LEN_SEL[0]
0
1
0
1
G52207-0, Rev. 3.0
4/3/98
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
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