VITESSE
SEMICONDUCTOR CORPORATION
155/622 Mhz 16 Channel PRBS
Generator and Comparator.
Preliminary Datasheet
VSC8109
VSC8109 Functional Block Diagram (Receiver)
LEN_SEL[1:0]
16
PRBS
16
RCK+/-
ERROR
16
DATA[15:0]
FRAME
ACCUMULATOR
Hold
ERR_C[8:0]
LOAD_PAT
DETECTION
CNT_SEL[1:0]
GATE_SEL
GATE
Transmitter Functional Description
The VSC8109 transmitter has four internal operating modes plus a bypass mode. When the bypass mode is
selected, the XDATA[15:0] is pipelined 3 TCK+/- clock cycles inside the chip before it appears on the output,
but is otherwise unchanged. The four internal modes are selected using OUT_SEL[1:0] (See Table 1).
Table 1: Internal Modes.
Internal Mode
PRBS Mode
PRBS With Frame Mode
Static Signal Mode
Square Wave Generation
Mode
OUT_SEL[1]
0
0
1
1
OUT_SEL[0]
0
1
0
1
Each of the Q[15:0] output channels can independently select XDATA or one of the four internal modes.
These settings are configured by using the bypass control register. The WRD_SRC[7:0] data bus is set to the
desired functionality and latched into the registers controlling the output mux. This is done with a clock pulse
on the LD_SRC_U and LD_SRC_L inputs. LD_SRC_U sets channels Q[15:8] and LD_SRC_L sets channels
Q[7:0]. A logic ‘1’ in a particular bit position forces that output to transmit pipelined XDATA, a logic ‘0’ selects
an internal transmitter signal.
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52207-0, Rev. 3.0
4/3/98
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
