VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
VSC8025/VSC8026
Mux/Demux and Section Terminator IC Chipset
Power Supply Sequencing
The +3.3V supply should not be allowed to remain in the absence of the -2.0V supply. If the -2.0V supply should
fault during the system operation, provisions should be made to sense this condition and turn off the -3.3V supply
within 1 second.
Power Supply Decoupling
This is a summary of the recommended bypass and decoupling components. The listed components should
be used for each VSC8025 and VSC8026 part. Component placement under the TBGA means on the back side
of the circuit board centered under the device.
VTT (-2V)
This supply is quiet, the entire core operates off current steering logic, with the exception of the ECL I/O
macros. However, the vast majority of it’s switching current comes from the external 50Ω pull down resistors
through the output FET to ground.
• Quantity (2) - 0.001µF low inductance (0603/0403 pkg) ceramic SMT X7R capacitors, placed under
TBGA as close to the V balls as possible.
TT
• Quantity (6) - 0.01µF HF low inductance (0603/0403 pkg) ceramic SMT X7R capacitor. Two of the six
should be placed under the TBGA.
• Quantity (6) - 0.1µF HF low inductance (0603 pkg) ceramic SMT X7R capacitor. Two of the six should be
placed under the TBGA.
LF Decoupling: 47µF tantalum low inductance SMT caps are sprinkled over the boards main -2V plane.
VTTL (+3.3V)
This is a particularly important power supply because it contains the only switching currents due mostly to
the TTL and some to the ECL I/Os. All core cells use current steering logic. The High speed core logic called
SCFL (Series Coupled FET Logic), similar to ECL, operates off the -2V VTT to the +3.3V VDD supply. The
same is true for the low speed logic called DCFL (Direct Coupled FET Logic) which operates from -2V to 0V.
Because the SCFL uses +3.3V its supplied through dedicated VDD Pins which should be filtered through a C-
L-C filter. There is usually only one digital +3.3V supply, so all other +3.3V supplies of concern must be filtered
to keep the noise from the +3.3V digital switching power supply out.
• Quantity (3) - 0.01µF HF low inductance (0603/0403 pkg) ceramic SMT X7R capacitor. Place two under
the TBGA.
• Quantity (8) - 0.1µF HF low inductance (0603 pkg) ceramic SMT X7R capacitor. Place two under the
TBGA.
• Quantity (3) - 1.0µF HF low inductance (0603 pkg) ceramic SMT X7R capacitor.
LF Decoupling: 47µF tantalum low inductance SMT are sprinkled over the board main +3.3V plane and
placed close to the C-L-C pie filter.
VDD (+3.3V)
As explained above this is the top rail to the SCFL core logic and must be filtered through a C-L-C pie filter.
• Quantity (1) - 0.01µF low inductance (0603 pkg) ceramic SMT X7R capacitor. Placed under the TBGA as
close to the V pins as possible.
DD
• Quantity (1) - 0.1µF HF low inductance (0603 pkg) ceramic SMT X7R capacitor. Placed under the TBGA
as close to the V pins as possible.
DD
Page 38
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52182-0, Rev. 4.0
1/5/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
