VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
2.488 Gb/s ATM/SDH/SONET STM-16/STS-48
Mux/Demux and Section Terminator IC Chipset
VSC8025/VSC8026
Application Notes
The byte clocks (TXCLK12[A:D] and TXCLKIN) on the VSC8025 have been brought off-chip to allow as
much flexibility in system-level clocking schemes as possible. Refer to Figure 4 & Figure 5 for connection
examples.
Interconnecting the VSC8025 Byte Clocks (TXCLK12[A:D] and TXCLKIN)
Contra-Directional Timing Mode
In this mode, the byte clock (TXCLK12A) clocks both the VSC8025 and data interface devices. It is impor-
tant to pay close attention to the routing of this signal. The PMC devices are CMOS parts which can have very
wide spreads in timing (2ns-11ns clock in to parallel data out for the PM5355) which utilizes most of the 12.86
ns period (at 77.76 MHz), leaving little for the trace delays and set-up times required to interconnect the
devices. The recommended configuration of PMC devices is to route TXCLK12A to all four devices in a star
like pattern; keep route lengths short, and tap TXCLKIN from a point which will match the net length to that of
data interface device connections. TXCLK12[B:D] can be used to simplify clock distribution and improve sig-
nal integrity; however, it is important to verify setup and hold values for each data interface using the route
lengths, clock skew, and any other system variables.
Co-Directional Timing Mode
In the co-directional mode an internal data synchronizing circuit is used to optimize the phase relationship
between a supplied TXCLKIN and internal clocks. The TXCLKIN signal needs to meet setup and hold timing
relative to the data stream and frame pulses, duty cycle, and 2.5GHz (or 311MHz) frequency lock.
Equipment and Facility Loopbacks
In order to create an Equipment Loopback, the EQULOOP VSC8026 input is held high. The byte-wide
STM-16/STS-48 data on the VSC8025 TXPOUT [7:0] outputs is clocked into the VSC8026 RXPIN [7:0]
inputs with the TXPCLKOUT clock. A frame pulse aligned with the first payload byte on the TXPOUT [7:0]
databus is provided to assure proper alignment. Both the Facility and the Equipment Loopbacks can be enabled
simultaneously. It is possible to disable (hold at a logic low) the serial high-speed outputs on the VSC8026 by
holding the asynchronous FACLOOP input low.
The diagram below (Figure 21) shows how an Equipment and a Facility Loopback are created. When in
Facility Loopback mode (FACLOOP is held high) the serial 2.488 Gb/s data and clock from the receive optics
module is first clocked into the VSC8026 and then fed back into the VSC8025 through TXSLBIN and TXSLB-
CLK. The FACLOOP input (held high) selects the data from the VSC8026 instead of the data from the 8:1 Mux.
The result is a line loopback from the receive optics module back out to the transmit optics module.
On-Chip Terminations
The VSC8025 and VSC8026 provide on chip terminations for the HSECL inputs as shown in Figure 22.
When using AC coupled input signals a 0.1µF capacitor is recommended on the REF points.
G52182-0, Rev. 4.0
1/5/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 37
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