VSC7123
Datasheet
Package Information
The VSC7123 device is available in the following package types, including lead-free packages:
●
●
●
●
VSC7123RD is a 64-pin, plastic thin quad flat pack (TQFP) with an exposed pad, 10 mm × 10 mm body size,
1 mm body thickness, and 0.5 mm pin pitch. VSC7123XRD is the lead-free package.
VSC7123YW is a 64-pin, plastic thin quad flat pack (TQFP) with an exposed pad, 14 mm × 14 mm body size,
1 mm body thickness, and 0.8 mm pin pitch. VSC7123XYW is the lead-free package.
VSC7123QU is a 64-pin, thermally enhanced, plastic quad flat pack (QFP) with a 10 mm × 10 mm body size,
2 mm body thickness, and 0.5 mm pin pitch.
VSC7123QN is a 64-pin, thermally enhanced plastic quad flat pack (QFP) with a 14 mm × 14 mm body size,
2 mm body thickness, and 0.8 mm pin pitch. VSC7123XQN is the lead-free package.
Lead-free products from Vitesse comply with the temperatures and profiles defined in the joint IPC and JEDEC
standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
Thermal Specifications
Thermal specifications for this device are based on the JEDEC standard EIA/JESD51-2 and are modeled using an
eight-layer test board. For more information, see the IPC and JEDEC standard.
Table 9. Thermal Resistances
θ
0
JA (°C/W) vs. Airflow (ft/min)
Part Number
VSC7123RD
VSC7123XRD
VSC7123YW
VSC7123XYW
VSC7123QU
VSC7123QN
VSC7123XQN
θJC
7
100
62.3
62.3
61
200
64.5
64.5
63
59.5
59.5
58
7
6
6
63
61
58
16
14.5
14.5
40
34
32
38
32
29
38
32
29
To achieve results similar to the modeled thermal resistance measurements, the guidelines for board design described
in the JEDEC standard EIA/JESD51 series must be applied. For information about specific applications, see the
following:
EIA/JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment
Mechanisms
EIA/JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
EIA/JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
EIA/JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements
EIA/JESD51-11, Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements
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G52212-0 Revision 4.7
March 14, 2008
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
