VSC7123
Datasheet
Pin Identifications
Table 8. Pin Descriptions
Pin #
2,3,4,6
7,8,9,11
12,13
22
Name
T0,T1,T2,T3
T4,T5,T6,T7
T8,T9
Description
INPUTS - TTL:
10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of REFCLK.
The data bit corresponding to T0 is transmitted first.
REFCLK
INPUT - TTL:
This rising edge of this clock latches T(0:9) into the input register. It also provides the reference
clock, at one-tenth the baud rate to the PLL.
62, 61
TX+, TX–
OUTPUTS - Differential PECL (AC-coupling recommended):
These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH,
TX+ is HIGH and TX– is LOW.
45,44,43,41
40,39,38,36
35,34
R0,R1,R2,R3
R4,R5,R6,R7
R8,R9
OUTPUTS - TTL:
10-bit received character. Parallel data on this bus is clocked out on the rising edges of RCLK
and RCLKN. R0 is the first bit received on RX+/RX–.
19
EWRAP
INPUT - TTL:
LOW for normal operation. When HIGH, an internal loopback path from the transmitter to the
receiver is enabled. TX+ is held HIGH and TX– is held LOW.
54, 52
31, 30
24
RX+, RX–
INPUTS - Differential PECL (AC-coupling recommended):
The serial receive data inputs selected when EWRAP is LOW. Internally biased to VDD / 2,
with 3.3 KΩ resistors from each input pin to VDD and GND.
RCLK,
RCLKN
OUTPUT - Complementary TTL:
Recovered clocks derived from 1/20th of the RX data stream. Each rising transition of RCLK
or RCLKN corresponds to a new word on R(0:9).
ENCDET
COMDET
INPUT - TTL:
Enables COMDET and word resynchronization when HIGH. When LOW, keeps current word
alignment and disables COMDET.
47
OUTPUT - TTL:
This output goes HIGH for half of an RCLK period to indicate that R(0:9) contains a comma
character (‘0011111XXX’). COMDET goes HIGH only during a cycle when RCLKN is rising.
COMDET is enabled by ENCDET being HIGH.
26
SIGDET
OUTPUT - TTL
SIGnal DETect. This output goes HIGH when the RX input contains a valid Fibre Channel or
Gigabit Ethernet signal. A LOW indicates an invalid signal.
16, 17
CAP0, CAP1
TCK
ANALOG: Differential capacitor for the CMU’s VCO, 0.1 μF nominal.
INPUT - TTL: JTAG clock input. Not normally connected.
INPUT - TTL: JTAG data input. Not normally connected.
INPUT - TTL: JTAG mode select input. Normally tied to VDDD
INPUT - TLL: JTAG reset input. Tie to VSSD for normal operation.
OUTPU - TTL: JTAG data output. Normally tri-stated.
Analog power supply
49
48
TDI
55
TMS
56
27
TRSTN
TDO
18
VDDA
VSSA
VDDD
15
Analog ground
5,10,20,23
28,50,57,59
Digital logic power supply
1,14,21,25
51,58,64
VSSD
Digital logic ground
29, 37, 42
32, 33, 46
60,63
VDDT
VSST
VDDP
N/C
TTL output power supply
TTL output ground
PECL I/O power supply
No internal connection
53
14 of 22
G52212-0 Revision 4.7
March 14, 2008
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
