VSC6134
Datasheet
3.2.6
3.2.7
3.2.8
3.2.9
LOHM BIP-8 Error Counter (LSW) Register.......................................................... 230
LOHM BIP-8 Block Error Counter (MSW) Register............................................... 230
LOHM BIP-8 Block Error Counter (LSW) Register................................................ 231
LOHM K1 and K2 Byte Validated Register............................................................ 231
3.2.10 LOHM S1 Byte Validated Register........................................................................ 231
3.2.11 LOHM M1 Byte Counter (MSW) Register ............................................................. 232
3.2.12 LOHM M1 Byte Counter (LSW) Register .............................................................. 232
3.2.13 LOHM E2 Byte Orderwire Register ....................................................................... 232
Section Overhead Monitor Registers .................................................................................. 233
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
SOH Monitor Z0 Byte Registers............................................................................ 233
BER Monitor Configuration Register ..................................................................... 233
BER Monitor Signal Degrade Monitored Frames (MSW) Register ....................... 234
BER Monitor Signal Degrade Monitored Frames (LSW) Register ........................ 234
BER Monitor Signal Degrade Error Threshold (MSW) Register............................ 234
BER Monitor Signal Degrade Error Threshold (LSW) Register............................. 235
BER Monitor Signal Degrade Clear Threshold (MSW) Register........................... 235
BER Monitor Signal Degrade Clear Threshold (LSW) Register............................ 235
BER Monitor Signal Degrade Error Decrement Register ...................................... 236
3.3.10 BER Monitor Signal Fail Monitored Frames (MSW) Register ............................... 236
3.3.11 BER Monitor Signal Fail Monitored Frames (LSW) Register ................................ 236
3.3.12 BER Monitor Signal Fail Error Threshold (MSW) Register.................................... 237
3.3.13 BER Monitor Signal Fail Error Threshold (LSW) Register..................................... 237
3.3.14 BER Monitor Signal Fail Clear Threshold (MSW) Register................................... 237
3.3.15 BER Monitor Signal Fail Clear Threshold (LSW) Register.................................... 238
3.3.16 BER Monitor Signal Fail Error Decrement Register .............................................. 238
3.3.17 J0 Monitor Valid Message Registers..................................................................... 238
3.3.18 J0 Monitor Control Register................................................................................... 239
3.3.19 TIM Control Register ............................................................................................. 240
3.3.20 SOH Monitor DCC Message Registers................................................................. 240
3.3.21 SOH Monitor Interrupt Mask Register ................................................................... 241
3.3.22 SOH Monitor Interrupt Status Register.................................................................. 242
3.3.23 B1 Block Error One Second Count Register ......................................................... 243
3.3.24 B1 Bit Error One Second Count Register.............................................................. 243
3.3.25 E1 Byte Register ................................................................................................... 243
3.3.26 F1 Byte Register.................................................................................................... 244
Line Overhead Generator Registers ................................................................................... 245
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
TX LOH Generator General Configuration Register.............................................. 245
LOH Generator K1 and K2 Bytes Configuration Register ..................................... 246
TX LOH Generator S1 Byte Configuration Register.............................................. 247
LOH Generator B2 Error Configuration Register................................................... 247
LOH Generator M0 and M1 Error Configuration Register..................................... 247
LOH Generator Source Configuration Register..................................................... 248
TX LOH Generator E2 Byte Configuration Register.............................................. 249
TX LOH Generator Line DCC Bytes Configuration Registers............................... 249
TX LOH Generator E2 and Line DCC Interrupt Mask Register............................. 249
3.4.10 TX LOH Generator E2 and Line DCC Interrupt Status Register ........................... 250
Section Overhead Generator Registers.............................................................................. 251
3.5
3.5.1
3.5.2
3.5.3
3.5.4
SOH Generator Z0 Byte Registers........................................................................ 251
SOH Generator J0 Byte Registers ........................................................................ 251
SOH Generator DCC Byte Registers .................................................................... 251
SOH Generator F1 Byte Registers........................................................................ 252
7 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
