VSC6134
Datasheet
Contents
Features..................................................................................................................................................... 1
Applications.............................................................................................................................................. 1
General Description ................................................................................................................................. 1
Revision History ..................................................................................................................................... 27
1
Product Overview............................................................................................................................. 35
1.1
Device Features.................................................................................................................... 35
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
SONET/SDH Interface Features ............................................................................. 35
Line-Side EFEC/OTU Interface Features................................................................ 36
Forward Error Correction (FEC) Features............................................................... 36
Client-Side OTU Interface Features........................................................................ 36
Ethernet Monitor Features....................................................................................... 37
General Features .................................................................................................... 37
1.2
FEC Algorithms and Performance ........................................................................................ 38
1.2.1
1.2.2
Reed Solomon FEC ................................................................................................ 38
EFEC....................................................................................................................... 40
1.2.2.1 Framing Structure and Interleaving............................................................ 40
BCH Codes ............................................................................................................. 41
1.2.3.1 Iterative Decoding with Concatenated Codes............................................ 42
1.2.3.2 Error Correcting Performance.................................................................... 42
1.2.3
2
Functional Descriptions .................................................................................................................. 45
2.1
Line Overhead Monitor.......................................................................................................... 48
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
B2 BIP-8 Line Error Monitor .................................................................................... 50
K1, K2 Automatic Protection Switching (APS) Monitor ........................................... 50
S1 Byte Synchronization Status Monitor................................................................. 52
M0 and M1 Remote Error Indication Monitor .......................................................... 52
Line DCC Monitor (D4 to D12) ................................................................................ 53
E2 Byte Monitor....................................................................................................... 53
LOH Monitor Register Information........................................................................... 53
2.2
Section Overhead Monitor .................................................................................................... 54
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
B1 BIP-8 Monitor..................................................................................................... 56
Bit Error Rate (BER) Monitor................................................................................... 57
J0 Monitor................................................................................................................ 58
E1, F1 Monitor......................................................................................................... 59
Section DCC Monitor (D1 to D3)............................................................................. 59
Z0 Extraction ........................................................................................................... 59
SOH Monitor Register Information .......................................................................... 60
2.3
2.4
Tx Transport Overhead Insertion Block ................................................................................ 61
2.3.1 Tx Overhead Insertion Port Timing ......................................................................... 61
Line Overhead Generator ..................................................................................................... 64
2.4.1
2.4.2
AIS-P Generator...................................................................................................... 66
B2 Generator and Error Insertion............................................................................ 67
3 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
