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    VSC6134XST-01 参数 Datasheet PDF下载

    VSC6134XST-01图片预览
    型号： VSC6134XST-01
    PDF下载： 下载PDF文件 查看货源
    内容描述： [Micro Peripheral IC,]
    分类和应用：
    文件页数/大小： 438 页 / 4019 K
    品牌： VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
     浏览型号VSC6134XST-01的Datasheet PDF文件第1页浏览型号VSC6134XST-01的Datasheet PDF文件第2页浏览型号VSC6134XST-01的Datasheet PDF文件第3页浏览型号VSC6134XST-01的Datasheet PDF文件第4页浏览型号VSC6134XST-01的Datasheet PDF文件第6页浏览型号VSC6134XST-01的Datasheet PDF文件第7页浏览型号VSC6134XST-01的Datasheet PDF文件第8页浏览型号VSC6134XST-01的Datasheet PDF文件第9页  
    VSC6134
    Datasheet
    2.8
    2.9
    2.10
    2.11
    2.12
    2.7.8
    FEC Scrambler...................................................................................................... 103
    2.7.9
    Test Error Injection ................................................................................................ 104
    2.7.10 Test PRBS Generation.......................................................................................... 105
    2.7.11 FEC Encoder Bypass Multiplexer.......................................................................... 105
    2.7.12 FEC Encoder Registers......................................................................................... 105
    Forward Error Correction (FEC) Decoder ........................................................................... 106
    2.8.1
    FEC Descrambler.................................................................................................. 107
    2.8.2
    BCH Decoder (Enhanced FEC) ............................................................................ 107
    2.8.3
    Deinterleaving Buffer............................................................................................. 110
    2.8.4
    Reed Solomon Decoder ........................................................................................ 110
    2.8.5
    Interleaving Buffer / EFEC Adapter ....................................................................... 112
    2.8.6
    Muxes.................................................................................................................... 113
    2.8.7
    Clock Crossing Buffer............................................................................................ 113
    2.8.7.1 General Operation ................................................................................... 114
    2.8.7.2 FIFO Spill Detection................................................................................. 114
    2.8.7.3 Asynchronous Demapping....................................................................... 114
    2.8.7.4 Rate Locked Loop (RLL) Controller ......................................................... 115
    2.8.8
    FEC Decoder Register Information ....................................................................... 117
    Digital Wrapper Overhead Processor and FEC Performance Monitor................................ 118
    2.9.1
    Digital Wrapper Overhead Format ........................................................................ 118
    2.9.2
    Status Bits ............................................................................................................. 119
    2.9.3
    Performance Monitoring ........................................................................................ 119
    2.9.4
    Serial Interfaces .................................................................................................... 121
    2.9.4.1 Digital Wrapper Overhead Serial Interface .............................................. 121
    2.9.4.2 Extracted Stuff Column Bytes Serial Interface......................................... 123
    2.9.5
    Overhead Processing............................................................................................ 124
    2.9.5.1 MFAS Monitor .......................................................................................... 124
    2.9.5.2 OTUk Section Monitor (SM)..................................................................... 124
    2.9.5.3 ODUk Tandem Connection Monitoring (TCM)......................................... 127
    2.9.5.4 ODUk TCM Activation/Deactivation Coordination (TCM ACT) ................ 130
    2.9.5.5 ODUk Path Monitoring (PM) Overhead ................................................... 130
    2.9.5.6 ODUk Automatic Protection Switching and Protection Control Channel . 133
    2.9.5.7 ODUk Fault Type and Fault Location Reporting Channel (FTFL)............ 133
    2.9.5.8 GCCx Extraction ...................................................................................... 134
    2.9.5.9 ODUk Experimental Overhead (EXP)...................................................... 135
    2.9.5.10 ODUk Reserved Overhead (RES) ........................................................... 135
    2.9.5.11 OPUk Payload Structure Identifier (PSI).................................................. 135
    2.9.5.12 OPUk Justification Bytes.......................................................................... 136
    2.9.5.13 Framed PRBS Monitor............................................................................. 136
    2.9.5.14 Generic AIS Monitor................................................................................. 136
    2.9.5.15 OTUk AIS Monitor.................................................................................... 136
    2.9.5.16 BDI Transmission to the DW Overhead Generator.................................. 136
    2.9.5.17 BEI Transmission to the DW Overhead Generator.................................. 137
    2.9.6
    DW Overhead Processor and FEC Performance Monitor Register Information ... 137
    10-GbE Receiver Monitor.................................................................................................... 138
    2.10.1 10-GbE MPU Interface and MIB/RMON Block ...................................................... 138
    2.10.2 10-GbE Receiver Monitor Register Information .................................................... 139
    Frame Aligner for SONET, ODU, and OTU Frames ........................................................... 140
    2.11.1 Frame Aligner for SONET/ODU/OTU Frames Register Information ..................... 144
    Phase-Frequency Discriminator.......................................................................................... 145
    2.12.1 Phase/Frequency Discriminator Register Information ........................................... 145
    Downloaded by pm_virendrakumar@yahoo.com on June 7, 2007 from Vitesse.com
    5 of 438
    VMDS-10185 Revision 4.0
    July 2006

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