VSC6134
Datasheet
Table 154. Add Encoder General Configuration Register 1 (continued)
Reset
Value
Bit
Name
Access
Description
1
FECENC_SCRENA
R/W
1: Configures the FEC scrambler to scramble the outgoing
1
data.
0: Configures the FEC scrambler not to scramble the
outgoing data.
0
SCRAM_MODE
R/W
1: Configures the FEC scrambler to scramble in the
G.975 format.
0
0: Configures the FEC scrambler to scramble in the
G.709 format.
3.6.2
Drop Encoder General Configuration Register 1
Address:
Register Reset Value:
0x280: Drop Path
0x2072
Table 155. Drop Encoder General Configuration Register 1
Reset
Value
Bit
Name
Access
Description
15:13
PM_STAT
R/W
If the PM field is provisioned for insertion, these bits are
inserted into the STAT bits of the PM field in the absence of
maintenance, alarm, or IAE conditions.
001
12
STUFF_CHAN_EN
R/W
When set to 1, data from an external FPGA is inserted into
the stuff columns of the OTU frame. Otherwise, zeros are
inserted or the stuff columns are used as data when in
Non-Stuff mode.
0
11:10
9:7
Reserved
RO
00
DROP_GCCG_CFG
R/W
Controls how the GCC2, GCC1, and GCC0 DW overhead
fields are created if the GCC is provisioned for insertion.
These bits are defined in Table 28, page 94.
000
6:4
3
Reserved
RO
111
0
DROP_TST_PRBS
R/W
1: A 231–1 PRBS sequence is inserted into the payload
area of OPU.
0: FEC encoder outputs normal OTU data.
2
1
DROP_TST_NULL
FECENC_SCRENA
R/W
R/W
1: A null pattern (all 0’s) is inserted into the OPU of the
outgoing OTU data.
0: FEC encoder outputs normal OTU data.
0
1
1: Configures the FEC scrambler to scramble the outgoing
data.
0: Configures the FEC scrambler to not scramble the
outgoing data.
0
SCRAM_MODE
R/W
1: Configures the FEC scrambler to scramble in the
G.975 format.
0
0: Configures the FEC scrambler to scramble in the
G.709 format.
256 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
