VSC6134
Datasheet
3.6
FEC Encoder Registers
The forward error correction (FEC) registers and configuration bits are shown in the following sections
for the add and drop side encoder blocks.The add side addresses begin with 0x800 and the drop side
begin with 0x280. The differences between the add and drop side registers are noted when necessary.
3.6.1
Add Encoder General Configuration Register 1
Address:
Register Reset Value:
0x800: Add Path
0x2072
Table 154. Add Encoder General Configuration Register 1
Reset
Value
Bit
Name
Access
Description
15:13
PM_STAT
R/W
If the PM field is provisioned for insertion, these bits are
inserted into the STAT bits of the PM field in the absence of
maintenance, alarm, or IAE conditions.
001
12
STUFF_CHAN_EN
R/W
When set to 1, data from an external FPGA is inserted into
the stuff columns of the OTU frame. Otherwise, zeros are
inserted or the stuff columns are used as data when in
Non-Stuff mode.
0
11:10
9:7
Reserved
RO
00
ADD_GCCG_CFG
R/W
Controls how the GCC2, GCC1, and GCC0 DW overhead
fields are created if the GCC is provisioned for insertion.
These bits are defined in Table 28, page 94.
000
6
5
4
AUTO_NFA_FIFOSPILL
FIFOSPILL_NFAONLOCK
NFA_FPRN
R/W
R/W
R/W
1: The upstream FEC frame aligner (dependent on data
path selected for add side) is forced to reframe and assert a
new NFA (or a FIFO pointer reset is asserted; see bit 4)
whenever a FIFO overflow or underflow is detected.
0: FIFO overflow or underflow is still detected and its alarm
asserted, but no action is taken.
1
1
1
1: If the AUTO_NFA_FIFOSPILL bit is high, a FIFO spill
detection forces a new NFA or a FIFO pointer reset (see
bit 4) only if PLL is in lock.
0: If the AUTO_NFA_FIFOSPILL bit is high, a FIFO spill
detection forces a new NFA or a FIFO pointer reset (see
bit 4) independent of the PLL lock status.
1: If the AUTO_NFA_FIFOSPILL bit is high, a new frame
alignment (NFA) is forced on a FIFO overflow or underflow.
0: If the AUTO_NFA_FIFOSPILL bit is high, a
FIFO_POINTER_RESET is forced on a FIFO overflow or
underflow.
3
2
ADD_TST_PRBS
ADD_TST_NULL
R/W
R/W
1: A 231–1 PRBS sequence is inserted into the payload
area of OPU.
0: FEC encoder outputs normal OTU data.
0
0
1: A null pattern (all zeros) is inserted into the OPU of the
outgoing OTU data.
0: FEC encoder outputs normal OTU data.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
