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VSC6134XST-01 参数 Datasheet PDF下载

VSC6134XST-01图片预览
型号: VSC6134XST-01
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC,]
分类和应用:
文件页数/大小: 438 页 / 4019 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VSC6134  
Datasheet  
2.15.13 Line FEC Regenerator Loopback Modes  
There are two Line FEC Regenerator Loopback modes:  
Line Side FEC Regenerator Loopback with Clock Management (with SONET Regen)  
Line Side FEC Regenerator Loopback with Clock Management (without SONET Regen)  
The following figure shows the Line Side FEC Regenerator Loopback mode. In this mode, LFEC data is  
received on the drop side, the signal is framed, decoded and optionally corrected, DWOH performance  
monitoring is performed, and the DWOH is terminated or passed through. A synchronously or  
asynchronously mapped SONET can be monitored and optionally regenerated. New DWOH is then  
inserted as required, and the LFEC parity bytes are recalculated and added. The received drop line  
Rxclk is internally looped back to the add Txclk.  
Figure 47. SONET Regenerator Mode  
164 of 438  
VMDS-10185 Revision 4.0  
July 2006