VSC6134
Datasheet
Figure 27. OPU Overhead
Synchronous
Mapping
Asynchronous
Mapping
15
16
15
16
17
1
2
3
4
1
2
3
4
RES
JC
RES RES
RES
RES
JC
JC
RES
RES
RES RES
RES RES
PSI NJO PJO
2.9.2
Status Bits
The overhead processor has many status bits. The configuration bit CLR_RD_WRN controls the
clearing of status bits. If CLR_RD_WRN is 1 (the default value), then a microprocessor read of a
register clears all the status bits in that register. If CLR_RD_WRN is 0, then a microprocessor write of a
1 to a status bit clears that status bit.
Most status bits have a live bit indicating the state of the status condition. Each live bit change of state
sets its respective status bit. Each status bit has its associated interrupt mask bit. The status bit and the
mask bit create a hardware interrupt to the microprocessor if the status bit is high and its associated
mask bit is low.
2.9.3
Performance Monitoring
The microprocessor interrupt status bits, EFEC_ERRS and StFEC_ERRS, and their associated interrupt
mask bits, EFEC_ERRM and StFEC_ERRM, flag bit errors in the respective enhanced and standard
FEC decoders. In addition to these status bits, the following bits flag errors in the individualist
Enhanced FEC decoders: EFEC4_ERRS, EFEC4_ERRM, EFEC3_ERRS, EFEC3_ERRM,
EFEC2_ERRS, EFEC2_ERRM, EFEC1_ERRS, and EFEC1_ERRM.
In Enhanced FEC mode (FEC_MODE_D = 1), the following 32-bit on-chip counters track various
errors:
●
●
EFEC_ZERO_ERR_UPR and EFEC_ZERO_ERR_LWR: Count of 0 errors, that is, a 1 is
transmitted, a 0 is received and corrected to a 1. (Note that this definition is opposite of that for
Standard FEC mode.)
EFEC_ONE_ERR_UPR and EFEC_ONE_ERR_LWR: Count of 1 errors, that is, a 0 is transmitted,
a 1 is received and corrected to a 0. (Note that this definition is opposite of that for Standard FEC
mode.)
●
●
●
EFEC_TOTAL_ERR_UPR and EFEC_TOTAL_ERR_LWR: Count of total corrected bit errors for
all four EFEC decoders.
EFEC4_ERR_UPR and EFEC4_ERR_LWR: Count of correctable bit errors (ones and zeros) from
decoder 4 (last decoder).
EFEC3_ERR_UPR and EFEC3_ERR_LWR: Count of correctable bit errors (ones and zeros) from
decoder 3.
119 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
