VSC6134
Datasheet
clock crossing FIFO. For example, eight negative justifications cause an extra words to be written into
the clock crossing FIFO. Conversely, eight positive justifications cause one less word to be written into
the clock crossing FIFO. The rate locked loop controller observes the fill levels in the clock crossing
FIFO and adjusts the frequency appropriately.
2.8.7.4
Rate Locked Loop (RLL) Controller
In the asynchronous demapping mode, a rate locked loop circuit is required to extract the CBR10G
(SONET/SDH) clock (622.08 MHz) from the received data. To facilitate this operation, a rate locked
loop (RLL) control block is provided on the device. The RLL controller block monitors the fill levels in
the clock crossing FIFO and generates pulses on output pins RLLUPP, RLLUPN, RLLDNP, and
RLLDNN. The following figure shows the RLL block and its connections.
Figure 22. Rate Locked Loop Block and Its Connections
PFD
Drop-Path
Clock-Crossing
FIFO
FEC Rate
Gapped Clock
Read Pointer
Write Pointer
RLL
Controller
1/4
VCO_MODE
FEC Decoder Block
RSOH Block
TXCLKSRC1
RLLUPP, RLLUPN
RLLDNP, RLLDNN
The RLL controller block along with an external low pass filter and VCXO constitute a rate locked loop.
The RLL controller block in the VSC6134 generates a train of up or down pulses to adjust the frequency
of the external VCXO. The rate and type (that is, up or down) of the pulses is dependent upon the
difference in rate of received CBR10G data and the VCXO clock frequency. This rate differential is
indicated by the fill level of the clock crossing FIFO. The RLL controller block monitors the fill level of
the clock crossing FIFO by sampling the read and write pointers at the end of every BCH or OTU row
(approximately every 3 μs). The pulses are generated to keep the pointers at an optimum distance from
each other.
The following figure shows the simplified schematic of the RLL controller block.
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
