VSC6134
Datasheet
Table 49. RXOCHD1 and RXOCHD0 Output Digital Wrapper Overhead Content (continued)
Cycle Number
341-468
Size
Description
16 bytes
4 bits
DW overhead from row #3
469-472
TCM3 BEI. For more information, see “BEI Transmission to the DW
Overhead Generator,” page 137.
473-476
477-480
481-484
4 bits
4 bits
4 bits
TCM2 BEI. For more information, see “BEI Transmission to the DW
Overhead Generator,” page 137.
TCM1 BEI.For more information, see “BEI Transmission to the DW Overhead
Generator,” page 137.
PM BEI. For more information, see “BEI Transmission to the DW Overhead
Generator,” page 137.
485-486
487-498
499-510
511-638
639
2 bits
Reserved (0b00)
12 bits
12 bits
16 bytes
1 bit
Corrected zero errors in the first two rows of OTU frame
Corrected one errors in the first two rows of OTU frame
DW overhead from row #4
BDI. For more information, see “BEI Transmission to the DW Overhead
Generator,” page 137.
640-655
656
16 bits
1 bit
Reserved (0x0000)
FIFO SMALL status (drop client clock crossing FIFO)
Total corrected bit errors in the current OTU frame
657-668
669-680
12 bits
12 bits
Uncorrectable codeword count from the final 4 k decoder in Enhanced FEC
mode or from the Reed Solomon decoder in Standard FEC mode, relevant to
the first two rows of OTU frame.
2.9.4.2
Extracted Stuff Column Bytes Serial Interface
The MTC6134 outputs extracted stuff column data using a serial interface. An FPGA interfaces to the
line side overhead processor and FEC performance monitor through the RXSTFD0 pin. The clock and
frame sync signals, DROPOHCLK0 and RXOCHFS0, are the same as those for the digital wrapper
overhead serial interface. For more information, see “Digital Wrapper Overhead Serial Interface,”
page 121. An FPGA interfaces to the client side overhead processor and FEC performance monitor
through the RXSTFD1 pin. The clock and frame sync signals, ADDOHCLK1 and RXOCHFS1, are the
same as those for the digital wrapper overhead serial interface. For more information, see “Digital
Wrapper Overhead Serial Interface,” page 121.
The following table describes the RXSTFD1 and RXSTFD0 content during the 680 cycles between
frame syncs (RXOCHFS0 and RXOCHFS1).
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
