VSC6134
Datasheet
2.8.5
Interleaving Buffer / EFEC Adapter
In Reed Solomon mode, the interleaving buffer performs the 16× byte-interleaving of the 255-symbol
Reed Solomon encoded codewords to produce FEC frames according to ITU-T G.709 and G.975
recommendations. After being interleaved, the data is forwarded to the clock crossing FIFO. In EFEC
mode this buffer acts as an elastic buffer that accepts writes from the EFEC decoder and translates into
an OTU frame type format before it goes to the clock crossing FIFO.
The interleaving buffer I/O descriptions are shown in the following table.
Table 46. Interleaving Buffer I/O Description
Name
Direction
Function
RESETN
CLK
IN
IN
IN
Active low reset.
194-MHz system clock.
PW_DN
Active high power down signal. When this signal is asserted, the
internal nodes of the interleaving buffer do not toggle.
CLK_EN
IN
IN
Out of seven clock cycles, this signal is high for six clock cycles of the
194 MHz clock and low for one clock cycle. This signal in combined with
the CLK input will be referred as the 167-MHz(CE)1 clock.
ENC_DATAO[63:0]
Output data bus from the encoder block at 167 MHz (CE). ENC_DATAO
is clocked out on the rising edge of the clock. Bit 63 is the MSB.
OOF
IN
IN
Active high signal indicating loss of alignment.
ENC_FSTARTO
Active high single-clock pulse from the FEC encoder block indicating
the first valid symbol of a Reed Solomon code.
RAM2_DATAO[63:0]
RAM2_SELECT
OUT
IN
Output data bus at 167 MHz (CE). RAM2_DATAO is clocked out on the
rising edge of CLK. Bit 63 is the MSB.
Active high select signal for selecting the interleaving block.
RAM2_RDATA[15:0] is 0 when RAM2_SELECT is low.
MPU_CLK
IN
IN
Microprocessor clock.
MPU_RESETN
MPU_RDENA
MPU_WRENA
MPU_WDATA[15:0]
MPU_ADDR[11:0]
RAM2_RDATA[15:0]
RAM2_INT
Active low MPU_CLK reset.
Microprocessor read enable signal.
Microprocessor write enable signal.
Microprocessor write input data bus.
Microprocessor address bus.
Read output data bus.
IN
IN
IN
IN
OUT
OUT
OUT
Active high interrupt signal.
Data acknowledgement pulse.
RAM2_DTK
1. 194-MHz clock with clock enable. The effective clock rate is 167-MHz.
112 of 438
VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
