VSC6134
Datasheet
2.8.1
FEC Descrambler
The FEC descrambler block descrambles the 64-bit wide FEC encoded data words using a frame
3
12
16
synchronous scrambler with a generating polynomial 1 + x + x + x + x in G.709 mode. This block
7
also has an optional G.975 mode that uses a generating polynomial 1 + x + x . The descrambler is reset
to FFFF (hex) all ones in G.709 mode and is reset to FEA9 (hex) 1111111010101001 in G.975 mode on
the first bit (MSB) that follows the last framing byte in the FEC frame (that is, the MSB of the MFAS
byte).The scrambler is disabled (data is passed through the block transparently) when the configuration
control bit DESCRAM_ENA is set to 0.
The descrambler block I/O is shown in the following table.
Table 43. FEC Descrambler Block I/O Description
Name
Direction
Function
RESETN
CLK
IN
IN
IN
Active low reset.
Standard FEC mode: 167-MHz system clock.
DATAI[63:0]
167-Mbps input data bus from the frame aligner block. DATAI is
clocked in on the rising edge of CLKI. Bit 63 is the MSB.
DATAO[63:0]
SCRENA
OUT
IN
167-Mbps output data bus. DATAO is clocked out on the rising
edge of CLKI. Bit 63 is the MSB.
When set to 1, scrambling is performed on the data. When set to
0, scrambling is bypassed.
FRAMESTART
G975_SCR
IN
IN
OTU frame sync coincident with word containing framing pattern.
High for G.975 mode and low for G.709 mode.
2.8.2
BCH Decoder (Enhanced FEC)
The BCH decoder, or enhanced FEC, exists on the drop line side of the VSC6134. For more
information, see “Product Overview,” page 35.
The I/O for the BCH decoder block is shown the following table.
Table 44. BCH Decoder Block I/O Description
Name
Direction
Function
CLK
IN
IN
IN
IN
IN
IN
IN
IN
IN
167-MHz system clock
Active low reset
RESET_N
N_FA
DATA_IN
OOF_IN
FRA_LINE_DATA_IN
FRA_LINE_NFA
FRA_LINE_FSTART
FECDEC_SCRENA
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VMDS-10185 Revision 4.0
July 2006
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
