VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
SC8164
Figure 7: Differential and Single Ended Input and Output Voltage Measurement
b
Single
= α
Ended
Swing
a
b
Different=ial α
Swing
a
* Differential swing (α) is specified as | b - a | ( or | a - b | ), as is the single ended swing.
Differential swing is specified as equal in magnitude to single ended swing.
Table 1: AC Characteristics
Parameters
Description
Min
Max
Units
Conditions
Data valid from falling
edge of CLK16O+
0
800
ps.
tpdd
CLK32O transition from
falling edge of CLK16O+
0
1.0
400
250
ns.
ps
ps
tpd32
D[15:0]+/- rise and fall
times
20% to 80% into 50 Ohm load.
See Figure 7
tDR, tDF
—
—
CLK16O+/- rise and fall
times
20% to 80% into 50 Ohm load.
See Figure 7
t
CLKR, tCLKF
% of
clock
cycle
CLK16OD
CLK16O+/- duty cycle
distortion
45
55
High speed clock input at 2.488GHz
DI+ setup time with respect
to falling edge of
HSCLKI+
tdsu
100
—
ps
ps
DI+ hold time with respect
to falling edge of
HSCLKI+
tdh
75
40
—
% of
clock
cycle
HSCLKID
HSCLKI+/- duty cycle
distortion
60
G52239-0, Rev. 3.3
5/17/00
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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