VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
VSC8164
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
recommended that the V power supply be decoupled using a 0.1µF and 0.01µF capacitor placed in parallel
CC
on each V power supply pin as close to the package as possible. If room permits, a 0.001µF capacitor should
CC
also be placed in parallel with the 0.1µF and 0.01µF capacitors mentioned above. Recommended capacitors are
low inductance ceramic SMT X7R devices. For the 0.1µF capacitor, a 0603 package should be used. The
0.01µF and 0.001µF capacitors can be either 0603 or 0402 packages.
For low frequency decoupling, 47µF tantalum low inductance SMT caps should be sprinkled over the
board’s main +3.3V power supply and placed close to the C-L-C pi filter.
If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling
V
must be changed to V , and all references to decoupling 3.3V must be changed to -3.3V.
EE
CC
AC Characteristics
Figure 5: AC Timing Waveforms
CLK16O+
Parallel data clock output
tpdd
D(0...15)+
VALID DATA (1)
VALID DATA (2)
Parallel data outputs
CLK32O+
tpd32
Parallel data clock output
Figure 6: High Speed Input Timing
DI+
D1 D2
D4 D5 D6 D7 D8 D9 D10D11 D12 D13D14 D15
D3
D0
High speed differential serial data input
HSCLKI+
High speed differential clock input
tdsu
tdh
Page 4
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52239-0, Rev. 3.3
5/17/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
