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SC8164 参数 Datasheet PDF下载

SC8164图片预览
型号: SC8164
PDF下载: 下载PDF文件 查看货源
内容描述: 2.488千兆位/秒至2.7Gbit /秒1时16 SONET / SDH的多路分离器 [2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux]
分类和应用:
文件页数/大小: 16 页 / 156 K
品牌: VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
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VITESSE
SEMICONDUCTOR CORPORATION
reliminary Datasheet
SC8164
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
High Speed Interface
The incoming 2.488Gb/s data (up to 2.7Gb/s for FEC applications) and input clock are received by high
speed inputs DI and HSCLKI. The data and clock inputs are internally terminated by a center-tapped resistor
network. For differential input DC coupling, the network is terminated to the appropriate termination voltage
V
Term
(pins HSDREF, HSCLKREF) providing a 50
to
V
Term
termination for both true and complement inputs.
For differential input AC coupling, the network is terminated to
V
Term
via a blocking capacitor.
In most situations these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit
topology, as shown in Figure 4. The reference voltage is created by a resistor divider as shown. If the input sig-
nal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be cen-
tered about this reference voltage and not exceed the maximum allowable amplitude (
V
CMI
,
V
IHSDC
).
For
single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage
which has better temperature and power supply noise rejection than the on-chip resistor divider. The external
reference should have a nominal value equivalent to the common mode switch point of the DC coupled signal,
and can be connected to either side of the differential gate.
Figure 4: High Speed Serial Clock and Data Inputs
Chip Boundary
V
CC
= 3.3V
Z
O
C
IN
50
C
AC
V
Term
C
IN
Z
O
50
V
EE
= 0V
C
IN
TYP = 100 nF
C
AC
TYP = 100 nF
Supplies
This device is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to
use the device in a ECL environment with a negative 3.3V supply, then VCC will be ground and VEE will be -
3.3V.
G52239-0, Rev. 3.3
5/17/00
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3