M1008
Preliminary
CMOS IC
TIMING SPECIFICATION
PARAMETER
3-Channel Pixel Rate
2-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulse Width
CDSCLK1 Pulse Width
CDSCLK2 Pulse Width
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Rising to CDSCLK1 Falling
ADCCLK Rising to CDSCLK2 Falling
Analog Sampling Delay
SYMBOL
TEST CONDITION
MIN TYP MAX UNIT
tPRA
tPRB
tPRC
tADCLK
tC1
100
66
40
16
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tC2
tC1C2
tADC1
tADC2
tAD
0
0
5
3-CHANNEL Mode Only
CDSCLK2 Falling to CDSCLK1 Rising
taC2C1
30
30
ns
ns
CDSCLK2 Falling to ADCCLK Rising
2-CHANNEL Mode Only
taC2ADR
CDSCLK2 Falling to ADCCLK Rising
CDSCLK1 Rising to ADCCLK Rising
CDSCLK2 Falling to CDSCLK1 Rising
1-CHANNEL Mode Only
tbC2ADR
tbC1ADR
tbC2C1
30
15
15
ns
ns
ns
CDSCLK2 Falling to ADCCLK Rising
CDSCLK1 Rising to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
SERIAL INTERFACE
tcC2ADR
tcC1ADF
tcC2C1
20
0
15
ns
ns
ns
Maximum SCLK Frequency
SLOAD to SCLK Setup Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Setup Time
SCLK Rising to SDARA Hold Time
Falling to SDATA Valid
fSCLK
tLS
tLH
tDS
tDH
10
10
10
10
10
10
MHz
ns
ns
ns
ns
tRDV
ns
DATA OUTPUT
Output Delay
Latency(Pipeline Delay)
tOD
8
9
ns
Cycles
UNISONIC TECHNOLOGIES CO., LTD
5 of 11
QW-R502-434.a
www.unisonic.com.tw
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