TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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6.4.12 MII Management Interface
Address
Length
(Byte)
Description
MII Management Interface
MII Management Control/Status
PHY Address
0x0510:0x0511
0x0512
2
1
1
2
1
1
4
0x0513
PHY Register Address
0x0514:0x0515
0x0516
PHY Data
MII Management ECAT Access State
MII Management PDI Access State
PHY Port Status
0x0517
0x0518:0x051B
Table 63: MII Management Interface Register Overview
6.4.12.1 MII Management Control/Status (0x0510:0x0511)
Bit
Description
ECAT
PDI
Reset Value
0
Write enable*:
r/(w)
r/-
0: Write disabled
1: Write enabled
This bit is always 1 if PDI has MI control.
1
2
Management Interface can be controlled by r/-
PDI (registers 0x0516:0x0517):
0: Only ECAT control
r/-
r/-
1: PDI control possible
MI link detection (link configuration, link detec- r/-
tion, registers 0x0518:0x051B):
0: Not available
1: MI link detection active
7:3
9:8
PHY address of port 0
r/-
r/-
Command register*:
r/(w)
r/(w)
Write: Initiate command.
Read: Currently executed command
Commands:
00: No command/MI idle (clear error bits)
01: Read
10: Write
Others: Reserved/invalid commands (do not
issue)
12:10 Reserved, write 0
r/-
r/-
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