TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
84 / 204
6.4.12.3 PHY Register Address (0x0513)
Bit
Description
ECAT
PDI
Reset Value
4:0
Address of PHY Register that shall be read/writ- r/(w)
ten
r/(w)
7:5
Reserved, write 0
r/(w)
r/(w)
Table 66: Register 0x0513 (PHY Register Address)
Note
r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is
generally blocked if Management interface is busy (0x0510.15=1).
6.4.12.4 PHY Data (0x0514:0x0515)
Bit
Description
ECAT
PDI
Reset Value
15:0
PHY Read/Write Data
r/(w)
r/(w)
Table 67: Register 0x0514:0x0515 (PHY Data)
Note
r/ (w): write access depends on assignment of MI (ECAT/PDI). Access is generally
blocked if Management interface is busy (0x0510.15=1).
6.4.12.5 MII Management ECAT Access State (0x0516)
Bit
Description
ECAT
PDI
Reset Value
31:0
Access to MII management:
0: ECAT enables PDI takeover of MII manage-
ment control
r/(w)
r/-
1: ECAT claims exclusive access to MII manage-
ment
31:0
Reserved, write 0
r/-
r/-
Table 68: Register 0x0516 (MI ECAT State)
Note
r/ (w): write access is only possible if 0x0517.0=0.
©2018 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany
Terms of delivery and rights to technical change reserved.
Download newest version at www.trinamic.com
TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
