TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
83 / 204
Bit
Description
ECAT
PDI
Reset Value
13
Read error:
0: No read error
r/(w)
r/(w)
1: Read error occurred (PHY or register not
available)
Cleared by writing to this register.
14
15
Command error:
r/-
r/-
r/-
r/-
0: Last Command was successful
1: Invalid command or write command without
Write Enable
Cleared with a valid command or by writing
"‘00"’ to Command register bits [9:8].
Busy:
0: MI control state machine is idle
1: MI control state machine is active
Table 64: Register 0x0510:0x0511 (MI Cntrl/State)
Note
r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is
generally blocked if Management interface is busy (0x0510.15=1).
* Write enable bit 0 is self-clearing at the SOF of the next frame (or at the end of the PDI access), Command
bits [9:8] are self-clearing after the command is executed (Busy ends). Writing "‘00"’ to the command
register will also clear the error bits [14:13]. The Command bits are cleared after the command is executed.
6.4.12.2 PHY Address (0x0512)
Bit
0:4
6:5
7
Description
ECAT
r/(w)
r/-
PDI
r/(w)
r/-
Reset Value
PHY Address
Reserved, write 0
Show configured PHY address of port 0-3 in r/(w)
register 0x0510.7:3. Select port x with bits [4:0]
of this register (valid values are 0-3):
0: Show address of port 0 (offset)
1: Show individual address of port x
r/(w)
Table 65: Register 0x0512 (PHY Address)
Note
r/ (w): write access depends on assignment of MI (ECAT/PDI). Write access is
generally blocked if Management interface is busy (0x0510.15=1).
©2018 TRINAMIC Motion Control GmbH & Co. KG, Hamburg, Germany
Terms of delivery and rights to technical change reserved.
Download newest version at www.trinamic.com
TRINAMIC [ TRINAMIC MOTION CONTROL GMBH & CO. KG. ]
