TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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6.4.7 Interrupts
6.4.7.1 ECAT Event Mask (0x0200:0x0201)
Bit
Description
ECAT
PDI
Reset Value
15:0
ECAT Event masking of the ECAT Event Request r/w
Events for mapping into ECAT event field of
EtherCAT frames:
r/-
0: Corresponding ECAT Event Request register
bit is not mapped
1: Corresponding ECAT Event Request register
bit is mapped
Table 40: Register 0x0200:0x0201 (ECAT Event M.)
6.4.7.2 AL Event Mask (0x0204:0x0207)
Bit
Description
ECAT
PDI
Reset Value
31:0
AL Event masking of the AL Event Request reg- r/-
ister Events for mapping to PDI IRQ signal:
0: Corresponding AL Event Request register bit
is not mapped
r/w
1: Corresponding AL Event Request register bit
is mapped
Table 41: Register 0x0204:0x0207 (AL Event Mask)
6.4.7.3 ECAT Event Request (0x0210:0x0211)
Bit
Description
ECAT
PDI
Reset Value
0
DC Latch event:
r/-
r/-
0: No change on DC Latch Inputs
1: At least one change on DC Latch Inputs (Bit is
cleared by reading DC Latch event times from
ECAT for ECAT controlled Latch Units, so that
Latch 0/1 Status 0x09AE:0x09AF indicates no
event)
1
2
Reserved
r/-
r/-
r/-
r/-
DL Status event:
0: No change in DL Status
1: DL Status change
(Bit is cleared by reading out DL Status
0x0110:0x0111 from ECAT)
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