TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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6.4.4 Data Link Layer
6.4.4.1 ESC Reset ECAT (0x0040)
Bit
Description
ECAT
PDI
Reset Value
Write
7:0
Reset is asserted after writing 0x52 (’R’), 0x45 r/w
(’E’), 0x53 (’S’) in this register with 3 consecutive
frames.
r/-
Read
1:0
Progress of the reset procedure:
01: after writing 0x52
10: after writing 0x45 (if 0x52 was written)
00: else
r/w
r/-
r/-
7:2
Reserved, write 0
r/-
Table 23: Register 0x0040 (ESC Reset ECAT)
6.4.4.2 ESC Reset PDI (0x0041)
Bit
Description
ECAT
PDI
Reset Value
Write
7:0
Reset is asserted after writing 0x52 (’R’), 0x45 r/-
(’E’), 0x53 (’S’) in this register with 3 consecutive
commands.
r/w
Read
1:0
Progress of the reset procedure:
01: after writing 0x52
10: after writing 0x45 (if 0x52 was written)
00: else
r/-
r/w
r/-
7:2
Reserved, write 0
r/-
Table 24: Register 0x0041 (ESC Reset PDI)
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