TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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Bit
Description
ECAT
PDI
Reset Value
18:16 RX FIFO Size (ESC delays start of forwarding r/w
r/-
until FIFO is at least half full). RX FIFO Size/RX
delay reduction** :
Value (for MII):
0: -40 ns
1: -40 ns
2: -40 ns
3: -40 ns
4: no change
5: no change
6: no change
7: default default
NOTE: EEPROM value is only taken over
at first EEPROM load after power-on or reset
19
EBUS Low Jitter:
r/w
r/-
0
0
0: Normal jitter / 1: Reduced jitter
21:20 Reserved, write 0
r/w
r/w
r/-
r/-
22
EBUS remote link down signaling time:
0: Default (≈660 ms)
1: Reduced (≈80 µs)
23
24
Reserved, write 0
r/w
r/w
r/-
r/-
Station alias:
0: Ignore Station Alias
1: Alias can be used for all configured address
command types (FPRD, FPWR, . . . )
31:25 Reserved, write 0
r/-
r/-
Table 25: Register 0x0100:0x0103 (DL Control)
* Loop configuration changes are delayed until end of currently received or transmitted frame at the port.
** The possibility of RX FIFO Size reduction depends on the clock source accuracy of the ESC and of every
connected EtherCAT/Ethernet devices (master, slave, etc.). RX FIFO Size of 7 is sufficient for 100ppm
accuracy, FIFO Size 0 is possible with 25ppm accuracy (frame size of 1518/1522 Byte).
6.4.4.4 Physical Read/Write Offset (0x0108:0x0109)
Bit
Description
ECAT
PDI
Reset Value
15:0
Offset of R/W Commands (FPRW, APRW) r/w
between Read address and Write address.
RD_ADR = ADR and WR_ADR = ADR + R/W-
Offset 0
r/-
Table 26: Register 0x0108:0x0109 (R/W Offset)
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