TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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Watchdog Register Set Once initialized, the watchdog timer monitors the application for activity and
allows setting of pre-programmed I/O patterns, in case the time limit is expired without activity.
In order to allow tuning of this time limit, the maximum time between two trigger events becomes
measured. This function also allows delay time measurement for input channels (i.e. when no watchdog
action is chosen). The watchdog timeout counter starts from zero up to WD_TIME. When it reaches
WD_TIME, it triggers the watchdog action.
The selected watchdog event resets the timeout counter. As trigger sources, the internal EtherCAT start
of frame (PDI_SOF), the two SPI chip select signals (PDI_SPI_CSN and MFC_CTRL_SPI_CSN) as well as any
combination of I/O lines can be used. For the I/O lines (MFCIO00 to MFCIO23), the polarity and edge are
programmable.
When using an MFCIOxx pin programmed as output and as watchdog trigger, the watchdog circuitry will
monitor the real output by checking the polarity of the output signal. This way, also a short circuit condition
will be detected. The chip select signals respond to a rising edge (i.e. when the SPI interface loads the SPI
shift register data into the corresponding registers).
Figure 50: Structure of the MFC IO watchdog unit
Watchdog Output Port Configuration The following table contains the assignments of ports/signals
to the configuration bits in the WD_OUT_MASK_POL register. An MFCIOxx pin programmed as output is
called MFCOxx.
Bit #
Signal
Bit #
32
Signal
0
1
2
3
4
5
6
7
8
MFCO00 polarity
MFCO01 polarity
MFCO02 polarity
MFCO03 polarity
MFCO04 polarity
MFCO05 polarity
MFCO06 polarity
MFCO07 polarity
MFCO08 polarity
MFCO00 mask
MFCO01 mask
MFCO02 mask
MFCO03 mask
MFCO04 mask
MFCO05 mask
MFCO06 mask
MFCO07 mask
MFCO08 mask
33
34
35
36
37
38
39
40
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