TMC8462 Datasheet • Document Revision V1.4 • 2018-May -09
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6.4.19.7 Latch1 Time Positive Edge (0x09C0:0x09C7)
Bit
Description
ECAT
PDI
Reset Value
63:0
Register captures System time at the positive r(ack)/- r/
0
edge of the Latch1 signal. (w
ack)*
Table 115: Register 0x09C0:0x09C7 (Latch1 Time Pos Edge)
Note
Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0]
are read, which guarantees reading a consistent value. Reading this register from
ECAT clears Latch1 Status 0x09AF.0 if 0x0980.5=0. Writing to this register from
ECAT is not possible.
* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if
0x0980.5=1 clears Latch1 Status 0x09AF.0. Writing to this register from PDI is not possible.
PDI register function acknowledge by Write command is enabled: Writing this register from PDI if
0x0980.5=1 clears Latch1 Status 0x09AF.0. Writing to this register from PDI is possible; write value is
ignored (write 0).
6.4.19.8 Latch1 Time Negative Edge (0x09C8:0x09CF)
Bit
Description
ECAT
PDI
Reset Value
63:0
Register captures System time at the negative r(ack)/- r/
0
edge of the Latch1 signal. (w
ack)*
Table 116: Register 0x09C8:0x09CF (Latch1 Time Neg Edge)
Note
Register bits [63:8] are internally latched (ECAT/PDI independently) when bits [7:0]
are read, which guarantees reading a consistent value. Reading this register from
ECAT clears Latch1 Status 0x09AF.0 if 0x0980.5=0. Writing to this register from
ECAT is not possible.
* PDI register function acknowledge by Write command is disabled: Reading this register from PDI if
0x0980.5=1 clears Latch1 Status 0x09AF.1. Writing to this register from PDI is not possible.
PDI register function acknowledge by Write command is enabled: Writing this register from PDI if
0x0980.5=1 clears Latch1 Status 0x09AF.1. Writing to this register from PDI is possible; write value is
ignored (write 0).
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